System and method for simplifying clock construction and analysis
US6721931B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor. The processor is configured by the software to: read a defined location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; read a defined number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; test electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes within the subset is equal, and change properties within the integrated circuit if the clock signal traversal time is not equal; and add the logical blocks to each of the interconnect routes within the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.