Lower latency coding/decoding
US6724327B1 · kind B1 · utility
13Cited by
4References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device may receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The pre-processing logic causes some of said codewords to be provided to the first decoder and other of said codewords to be provided to the second decoder. The codewords may be of different lengths and/or different code rates. Further, the first and second decoders may implement the same or different decoding technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.