Substrate-triggering of ESD-protection device
US6724592B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.