Multi-layer chip capacitor
US6724611B1 · kind B1 · utility
119Cited by
29References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Mar 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/85
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit thin film capacitor includes multiple layers of conductors separated by dielectric material. The conductive layers are connected to interconnect lands using conductive vias. The interconnect lands can be controlled collapse chip connection (C4) lands that allow the capacitor to be connected to a circuit board. In one embodiment, the capacitor is mounted on a circuit board in close proximity to a processor circuit. The multi layer capacitor of the present invention provides the ability to increase a capacitance value while lowering interconnect resistance and inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.