Latch inference using dataflow analysis
US6725187B1 · kind B1 · utility
2Cited by
7References
9Claims
0Family size
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Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Dec 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.