DEBUG mode for a data bus
US6725306B2 · kind B2 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Sep 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.