Memory system
US6725321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Mar 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.