Method and apparatus for preventing cache pollution in microprocessors with speculative address loads
US6725338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Jun 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the speculative load, and preventing use of the marked speculative load by the microprocessor if a miss occurs. A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, inserting the marked speculative load into a load miss queue, determining whether a miss occurs for the speculative load, and preventing the load miss queue from committing the marked speculative load to cache if a miss occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.