Method and apparatus for overlaying memory in a data processing system
US6725346B1 · kind B1 · utility
2Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes an embedded controller (100) having a core (102), a system bus, nonvolatile memory (104), and random access memory (RAM) (106). The RAM (104) has a non-overlay region (108) and an overlay region (110). The overlay region (110) may be divided into a plurality of partitions. Partitions of the overlay region (110) may be used as general purpose memory when they are not being used as overlay regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.