Method and apparatus for emulating a floating point stack in a translation process
US6725361B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Jan 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.