Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed
US6725387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (“GFC”) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.