Method and an apparatus for adjusting clock signal to sample data
US6725390B1 · kind B1 · utility
10Cited by
18References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Jan 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention includes a method to communicate a data packet. At a second input of a variable delay device, a first clock signal having at least one edge is received. At a first input of a detector, a first data packet having data that defines a second clock signal is received. At a second input of the detector, an output of the variable delay device is received. The output of the variable delay device is then compared to the second clock signal to produce an offset signal. The first clock signal is adjusted as a function of the offset signal to produce an output of the variable delay device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.