Efficient redundancy calculation system and method for various types of memory devices
US6725403B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1999 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Nov 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for calculating and analyzing redundancies for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region. It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered. A system, preferably for on-chip implementation is also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.