Pattern detection for computer segments
US6725420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0754
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.