Method of automated design and checking for ESD robustness
US6725439B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Apr 20, 2004 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.