Memory daughter card apparatus, configurations, and methods
US6726505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/184
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
New methods and configurations are provided that allow for a large memory capacity, as well as minimized interconnect distances between the memory chips and one or more processors, and the HUB chip-set. The apparatus, configurations and methods include providing a printed circuit board having one or more processor conductive portions and one or more z-axis connector conductive portions in close proximity with each other, and connecting the one or more processors on one side of a printed circuit board, and connecting the one or more z-axis connectors for the memory daughter cards on the opposite side of the processor board. Standoffs are used to support and secure the horizontally disposed z-axis memory daughter cards and to ensure proper spacing between the z-axis daughter cards and the processor board Standoffs include an alignment pin portion and a spacer portion. The alignment pin portion includes an alignment portion, foot, and urging portion. The spacer portion includes pin coupler, relief portion, and aperture. The standoff is inserted into an aperture of a first printed circuit board and turned 90 degrees to secure the spacer portion and the foot to the first printed circuit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.