Multi-step process for forming a barrier film for use in copper layer formation
US6727177B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method involves providing a substrate having an insulating layer with an opening therein configured to receive an inlaid conducting structure. A copper seed layer is formed on the insulating layer and in the opening. The seed layer is implanted with barrier material ions to form an implanted seed layer. Upon the implanted seed layer is formed a bulk copper-containing layer. The substrate is then annealed so that barrier material ions migrate through the seed layer to an interface between the seed layer and the insulating layer to form a final barrier layer. The barrier material can include palladium, chromium, tantalum, magnesium, and molybdenum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.