Three dimensional integrated circuits
US6727517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor crystal grains are formed by metal-induced lateral crystallisation. The positions of the grain boundaries normal to the crystallisation direction are controlled, to position the grains correctly for subsequent formation of electronic devices within them. In a first technique, the grains are positioned by depositing the metal in short strips which each induce the crystallisation of a single corresponding grain. In a second technique, the grains are positioned by pre-patterning the amorphous silicon which is used to form the grains. Electronic circuit elements can be formed in each grain. The resultant structure can be used in a microelectronic mechanical system. Several grains can be formed successively and circuit elements formed in each layer to form a three-dimensional integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.