Semiconductor device having triple well structure
US6727573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device according to the present invention comprises: a semiconductor substrate 10 of a first conductivity type; a well 28 of a second conductivity type different from the first conductivity type formed in a region 18 surrounding a region 20 of the semiconductor substrate 10; a diffused layer 42 of the second conductivity type formed, buried in the semiconductor substrate 10 in the region 20 and connected to the well 28 on a side thereof; and a well 44 of the first conductivity type formed in the semiconductor substrate 10 in the region 20 on the side of a surface thereof and electrically isolated from a rest region of the semiconductor substrate 10 by the well 28 and the diffused layer 42. This constitution of the semiconductor device permits the diffused layer 42 and the well 28 to be formed by the use of one and the same mask, whereby in electrically isolating the well 44 from the semiconductor substrate by the well 28 and the diffused layer 42, the triple well can be formed without increasing lithography steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.