High-voltage level shifting circuit with optimized response time
US6727742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A high-voltage level shifting circuit with optimized response time, comprising: an inverter having an input and an output, the inverter being connected between a first voltage and a second voltage whose difference remains constant over time; a resistor, in which one terminal is connected to the first voltage and a second terminal is connected to the input of the inverter; a high-voltage transistor, which is connected between the second terminal of the resistor and a current source whose switching on and off determine the level shifting of a digital signal; and a clamp transistor, which is connected between the first voltage and a node that is common to the resistor and to the high-voltage transistor. The gate terminal of the clamp transistor is connected to the output of the inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.