High speed, low power comparator
US6727839B2 · kind B2 · utility
7Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.