Redundant array architecture for word replacement in CAM
US6728123B2 · kind B2 · utility
3Cited by
10References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | May 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.