Semiconductor memory
US6728157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2003 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jan 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.