Switching apparatus comprising a centralized switch core and at least one SCAL element(s) for the attachment of various protocol adapters
US6728251B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.