Multi-processor system and its network
US6728258B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Dec 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.