Method and apparatus for simulated error injection for processor deconfiguration design verification
US6728668B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2736
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.