Heartbeat failure detector method and apparatus
US6728781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | May 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The Heartbeat Failure Detector of the present invention, is a new, simple method and device that has several identical modules, and each module is attached to a processor in the system. Roughly speaking, the module of a processor x maintains a heartbeat counter for every other process. For each process y, the counter of y at x (called the heartbeat of y at x) periodically increases while y is alive and in the same network partition, and the counter stops increasing after y crashes or becomes partitioned away. Using such a device, x can solve the communication problem above by resending m only if the heartbeat of y at x increases. Note that if y is crashed (or partitioned away from x), its heartbeat at x stops almost immediately, and so x will also immediately stop sending copies of m to y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.