DMA channel for high-speed asynchronous data transfer
US6728795B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2000 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Apr 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer, high speed asynchronous data can be manipulated by the DMA controller by use by other applications, such as wireless communication applications. The wireless communication applications includes Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), or Personal Digital Cellular (PDC). These wireless communication applications utilize high asynchronous data rates that would require more expensive USART with additional buffer capacity. In the receive mode, the high speed asynchronous data shifted into a DMA FIFO buffer from the USART. The data is then flushed into a host memory, such as a protocol stack by the DMA controller once the FIFO is full or if a timer expires. The data in the protocol stack is then manipulated by the wireless communication application. In the transmit mode, the high speed asynchronous data is similarly manipulated to provide data from the protocol stack to the USART.The present invention utilizes conventional hardware thus reducing cos…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.