Method and apparatus for controlling multi-channel bitstreams
US6728824B1 · kind B1 · utility
147Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for an incoming multi-channel bitstream including a computer memory having an address range, a plurality of memory controllers, and a selector coupling the memory controllers to the computer memory. Each memory controller is capable of providing an address within the address range of the computer memory. In use, the selector selects a memory controller based on a received data type in an incoming bitstream. The selector then provides an address received from the selected memory controller to the computer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.