SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
US6728845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.