Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component
US6728890B1 · kind B1 · utility
7Cited by
10References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Apr 20, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.