System and method for clock adjustment by subsequently detecting a target bit of data stream, re-adjusting, and correcting clock based on difference in detected bit
US6728894B2 · kind B2 · utility
6Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | May 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.