System and method for testing memory systems
US6728911B1 · kind B1 · utility
3Cited by
17References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for testing memory systems in accordance with the present invention increases efficiency and reduces initial diagnostic and power up time for microprocessor-based units. The method includes copying a test process sequence into a memory system; updating an address indicative of the segment of the memory system being tested; comparing the address to an end of memory system address; copying the test process sequence to a next block of the memory system, and iterating through the method until the addresses are equal and the end of the memory system is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.