Sequential test pattern generation using combinational techniques
US6728917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2001 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Jul 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318392
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines. Advantageously, the invention allows efficient combinational test pattern generation techniques to be applied to a sequential circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.