Error correcting method and apparatus
US6728925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 1999 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | May 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0075
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In an error correcting method and an apparatus therefor using Hamming codes, a frame regulated by a synchronous network is divided into L blocks in the direction of row. Preferably, information bits and check bits are allocated to a payload portion and non-defined bits of an LOH portion, respectively. More preferably, the information bits and the check bits are divided into M sub blocks to form a Hamming code block. In addition, a code error correcting means rearrange each Hamming code block per bit and further preferable, a syndrome register with a plurality of banks operates an error syndrome of the Hamming code block, and based on the operation result, the code error correction of the Hamming code block is performed by a bank switchover.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.