Method of modeling the crossover current component in submicron CMOS integrated circuits designs
US6728941B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Apr 27, 2004 |
| Priority date | — |
| Expiry date | Aug 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of calculating a crossover current component of dynamic power dissipation at a gate of a CMOS integrated circuit design is operable on a digital computer. The method includes deriving two constants. An effective width is computed for the gate, a transition time is computed at an input of the gate, an activity ratio is determined for the gate, and a load capacitance is computed at an output of the gate. The effective width is multiplied by the activity ratio, the clock rate, and the difference of the first constant multiplied by the transition time and the second constant multiplied by the load capacitance to determine a crossover current component of dynamic power of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.