Chip and defect tolerant method of mounting same to a substrate
US6730527B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is provided with a plurality of regions, at least one of which is operationally redundant. An integrated circuit to be placed onto the substrate has a plurality of functional units that are designed to be interchangeable. The integrated circuit is tested for defects and, if a functional unit is found to be defective, then the integrated circuit is oriented (e.g., rotated or translated) with respect to the substrate such that the defective functional unit overlies the operationally redundant region of the substrate. A functional association is then formed between the remaining regions of the substrate and the non-defective functional units of the integrated circuit. Such functional association may be achieved by connecting each pair of unit and region. In this way, an integrated circuit with defective functional unit need not be discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.