Complementary transistors with controlled drain extension overlap
US6730556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type that is complementary to the first conductivity type. The method includes the steps of forming a first gate stack (100), the first transistor including the first gate stack and forming a second gate stack (80), the second transistor including the second gate stack. The method further includes implanting a first drain extension region (107) at a first distance relative to the first gate stack, the first transistor including the first drain extension region, and the method includes implanting a second drain extension region (87) at a second distance relative to the second gate stack, the second transistor including the second drain extension region. The first distance is greater than the second distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.