Multiple thickness hard mask method for optimizing laterally adjacent patterned layer linewidths
US6730610B1 · kind B1 · utility
4Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Dec 20, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a pair of patterned target layers within a microelectronic product employs a pair of patterned etch mask layers of different thicknesses. The pair of patterned etch mask layers of different thicknesses provides that the pair of patterned target layers may be formed with individual linewidth control, absent fabrication or modification of a photomask to realize the same result. The method is particularly useful for fabricating pair of gate electrodes for use within CMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.