System and method for controlling a number of outstanding data transactions within an integrated circuit
US6731292B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.