Apparatus for analyzing a failure of a semiconductor device and method thereof
US6732062B2 · kind B2 · utility
2Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 2003 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | May 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an apparatus for analyzing a failure of a semiconductor device, a wafer map memory stores test result data of each test wafer. A failure die number/rate, a D/S good die number/yield and a FBM good die number/yield on each test mode of each test wafer are calculated. In case a failure bit mode to be defined is selected from a plurality of failure bit modes, a failure die rate for total dies and a failure die rate for total failure dies are calculated. An expected FBM yield, an expected D/S yield, an average D/S yield, and a maximum/minimum yield are calculated. The calculated values are displayed on a monitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.