Digital signal processor and digital signal processing system incorporating same
US6732132B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2001 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor (DSP) is disclosed which is capable of starting a new arithmetic operation even when results of completed arithmetic operations cannot be written into accumulators because they already contain results. The DSP includes an arithmetic operation unit, a bus, at least one accumulator and a bypass device. The bus transfers data to be processed by the arithmetic operation unit in addition to the results of arithmetic processing performed by the arithmetic operation unit. The at least one accumulator holds the results of arithmetic processing and delivers the results to the bus. The bypass device may contain a delay element that delays delivery of the results to the bus for the same length of time that it would take for the results to be delivered to the bus via the at least one accumulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.