Method and apparatus for accumulating partial quotients in a digital processor
US6732135B1 · kind B1 · utility
3Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital processor performing division, quotient accumulation apparatus is formed of a set of muxes and a single carry save adder. Partial quotients are accumulated in carry-save form with proper sign extension. Delay of partial quotient bit fragments from one iteration to a following iteration enables the apparatus to limit use to one carry save adder. By enlarging minimal logic, the quotient accumulation apparatus operates at a rate fast enough to support the rate of fast dividers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.