Multiple processor computer
US6732213B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Feb 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer is provided that has a plurality of insertion cards that are interconnected via a bus. One insertion card includes a local processing unit and a first intermediate memory for intermediate storage of messages intended for the local processing unit, and a second intermediate memory for intermediate storage of messages originating from the local processing unit. A third intermediate memory and a fourth intermediate memory are provided for free message locations that are intended for or originate from the local processing unit. The second and the third intermediate memories are each provided with a respective intermediate memory extension in a local memory of the local processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.