Network translation circuit and method using a segmentable content addressable memory
US6732227B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Sep 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L61/2596
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A translation circuit for translating addresses between computer networks and an associated method of performing address translation for a computer system are provided. The translation circuit includes a content addressable memory (CAM) device having a CAM array that is logically divided into a plurality of CAM segments. First and second sets of CAM segments are designated to perform comparison operations for addresses having first and second widths, respectively. An instruction provided to the CAM device specifies an address translation having either the first or second width. A comparison operation is performed in the first set of segments if the instruction specifies an address translation of the first width. A comparison operation is performed in the second set of segments if the instruction specifies an address translation of the second width. In one embodiment, each segment has the same size, and includes a plurality of sub-segments, each having the same width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.