Cache memory system and method for a digital signal processor
US6732235B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2000 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Nov 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention. The system further includes a cache memory system allowing one process to perform real-time digital signal processing according to a modifiable program stored in a modifiable non-volatile memory by temporarily loading portions of the program into a fast, local memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.