Multi-ported memory having pipelined data banks
US6732247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2001 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-ported pipelined memory is located on a processor die serving as an addressable on-chip memory for efficiently processing streaming data. The memory sustains multiple wide memory accesses per cycle, clocks synchronously with the rest of the processor, and stores a significant portion of an image. Such memory bypasses the register file directly providing data to the processor's functional units. The memory includes multiple memory banks which permit multiple memory accesses per cycle. The memory banks are connected in pipelined fashion to pipeline registers placed at regular intervals on a global bus. The memory sustains multiple transactions per cycle, at a larger memory density than that of a multi-ported static memory, such as a register file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.