Multiple address translations
US6732250B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | May 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.