Two stage detector having viterbi detector matched to a channel and post processor matched to a channel code
US6732328B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1999 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Jul 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/1863
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two-stage sampling data detector for a partial response channel having a channel code encoder for encoding user information sequences into blocks of code words in accordance with a predetermined channel block code characterized by a list of most likely error-events comprising impermissible code words. The detector includes a first-stage detector, such as a Viterbi detector, connected to receive samples from the partial response channel and matched to characteristics of the channel and not to the channel code, puts out unchecked bit estimates. A second stage post-processor checks the bit estimates in relation to derived detector decision metrics information and the channel block code, and puts out post-processed bit estimates to a channel code decoder after correcting detected erroneous sequences in accordance with the decision metrics information, information derived from the channel code, and the list of most likely error-events. A method for generating the channel block code is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.