Method for thin film resistor integration in dual damascene structure
US6734076B1 · kind B1 · utility
15Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2003 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Mar 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.